1. Field of the Invention
The present invention relates generally to high voltage switching, and more particularly to a more flexible system for switching between a low voltage and a high voltage at an adjustable ramp rate.
2. Description of Background of Art
An erasable programmable read-only memory ("EPROM") is a non-volatile integrated memory circuit, which stores data in memory cells constructed from enhancement-type n-channel metal-oxide semiconductor field effect ("NMOS") memory transistors. Each EPROM memory cell is one single memory transistor, which is logically organized into a memory array of aligned rows representing word lines and aligned columns representing bit lines. To select a memory cell for either programming or erasing, a row decoder and column decoder, each with separate high voltage switches corresponding to specific word lines and bit lines, activate the word line and bit line corresponding to the selected memory cell.
When a selected memory cell is programmed, the memory transistor of the memory cell is placed into the "0" logic state by lowering the threshold voltage level of the memory transistor to approximately 0.5V to 1V. When the memory cell is erased by a technique such as exposing the memory cell to UV light, the memory transistor is placed into the "1" logic state by increasing the threshold voltage level of the memory transistor to approximately 5V or higher.
Another type of memory device is an electrically erasable programmable read only memory ("EEPROM"). For EEPROMs, each EEPROM memory cell, unlike the EPROM memory cell, consists of two NMOS transistors, a "select" transistor and the memory transistor.
Typically, during the programming operation for the memory cells, a high voltage V.sub.pp of about 12 to 20 volts is transferred by the row and column decoders to the selected word line to turn "on" the select transistor of the selected memory cell. By further transferring V.sub.pp to the selected bit line attached to the drain electrode of the select transistor and approximately 0 volts to the control gate of the memory transistor, a small tunneling current lowers the threshold voltage of the memory transistor to approximately a range of 0.8V to -2V.
During the erasure operation, the control gate of the selected memory cell is raised to a high voltage V.sub.pp and the bit line of the selected memory cell is lowered to 0 volts. Since the floating gate is electrically isolated from the memory transistor, once the high voltage V.sub.pp is removed, a charge remains on the floating gate and the threshold voltage of the memory transistor is raised to at least approximately half of the read voltage V.sub.cc. V.sub.cc is approximately 1.5 to 6 volts.
To switch between memory cells to alter the logic states of these memory cells, the row and column decoders rely upon a plurality of high voltage NMOS switches to switch between a high and a low voltage level. FIG. 1A illustrates a high level schematic drawing of one of these conventional high voltage NMOS switch designs 100 which is electrically interconnected between the output of an input state logic circuit 115 and an input of a storage device 117 such as a memory array. To simplify the discussion, even though a plurality of high voltage NMOS switches 100 in conjunction with the input state logic circuit 115 comprise a decoder, only one of the high voltage NMOS switches 100 will be illustrated.
The high voltage NMOS switch 100 includes a switch 105, a high voltage pump 107, a power source 109, and a connection to ground 111. The switch 105 receives either a high or a low input logic state V.sub.state from an input state logic circuit 115, which the switch 105 in turn transforms into either a distinct low or high switch output voltage level V.sub.out for the storage device 117. It should be noted that the switch output voltage level V.sub.out can also be considered the output voltage level of the overall decoder, which is not shown.
For example, if V.sub.state is in a high or "1" logic state, the switch 105 connects a switch output node 125 with ground 111 resulting in the switch output voltage level V.sub.out dropping to 0 volts. If the switch 105 receives V.sub.state in a low or "0" logic state, the high voltage pump 107 ramps up V.sub.out to a high voltage output level V.sub.pp (e.g. 10-20V) based solely upon a first half-cycle of a power source waveform signal V.sub.ps, which is illustrated in FIG. 3. A more detailed description of the high voltage pump 107 will be discussed in FIG. 1B.
FIG. 1B is an illustration of a more detailed schematic drawing of the conventional high voltage switch 100 discussed in FIG. 1A. The high voltage switch 100 more specifically includes three transistor switches, M.sub.1, M.sub.2, M.sub.3, a clamping diode transistor M.sub.4, two high voltage pump transistor diodes, M.sub.5 and M.sub.6, a high voltage pump coupling capacitor, C.sub.p, and a power source 109.
The switch 105 discussed in FIG. 1A consists of NMOS transistor switches M.sub.1, M.sub.2, and M.sub.3. Transistors M.sub.1 and M.sub.2 have gate electrodes which are electrically coupled together with the input state logic circuit 115 at an input node 124. The source electrodes of M.sub.1 and M.sub.2 are electrically coupled to ground 111. The drain electrode of M.sub.1 is electrically coupled to the output of the high voltage pump 107 at node 123 as well as to the control gate electrode of transistor M.sub.3. The drain electrode of M.sub.2 is electrically coupled with the output node 125 which is also electrically coupled to the source gate of transistor M.sub.3. The drain electrode of transistor M.sub.3 is electrically coupled to the high voltage output level V.sub.pp.
As discussed above, when the input state logic circuit 115 transmits V.sub.state in a high logic state, transistor switches, M.sub.1 and M.sub.2 close and the output node 125 is connected directly with ground 111 resulting in V.sub.out dropping to 0 volts. When the input state logic circuit 115 transmits V.sub.state in a low logic state, M.sub.1 and M.sub.2 remain open, thereby allowing the high voltage pump 107 to begin ramping up V.sub.out to the high voltage output level V.sub.pp.
The high voltage pump 107 includes a clamping diode transistor M.sub.4, a coupling capacitor C.sub.p, and pumping transistor diodes, M.sub.5 and M.sub.6. C.sub.p is electrically coupled to the power source 109, which generates a power source waveform signal V.sub.ps having a first half-cycle at V.sub.cc (e.g. 5 volts) and a second half-cycle at 0 volts. As illustrated in FIG. 3, in the first half-cycle of the power source waveform signal V.sub.ps, the voltage level rises from 0 to V.sub.cc. During the second half-cycle of the power source waveform signal V.sub.ps, the voltage level drops from V.sub.cc to 0 volts. C.sub.p isolates the power source waveform signal V.sub.ps from the high voltage pump 107.
Pumping transistor diodes M.sub.5 and M.sub.6 receive the coupled power source waveform signal V.sub.ps and, as illustrated in FIG. 3, the switch output voltage level V.sub.out is ramped up to higher voltage levels during only the first half of the full ramp up potential of the switch 100. More specifically, since V.sub.ps continually alternates in half-cycles between a high voltage level V.sub.cc and 0 volts, the ramp up of V.sub.out only occurs during the first half-cycle (e.g. when the voltage level increases from 0 volts to V.sub.cc) of each full-cycle of V.sub.ps. The second half-cycle of V.sub.ps remains unused.
During this first half-cycle of V.sub.ps, V.sub.121 and V.sub.123 can be mathematically described using the following equations: EQU V.sub.121 =V.sub.ps (C.sub.1 /(C.sub.1 +C.sub.121)) EQU V.sub.123 =V.sub.121 -V.sub.TM5
where C.sub.1 is the capacitance of C.sub.p, C.sub.121 is the stray capacitance of node 121, V.sub.ps is approximately equal to V.sub.cc, and V.sub.TM5 is the threshold voltage for transistor diode M.sub.5. During the second half-cycle of V.sub.ps, no additional ramp up of V.sub.121 or V.sub.123 occurs.
After each full cycle of V.sub.ps, V.sub.121 and V.sub.123 continue to ramp up during only the first half-cycle of V.sub.ps toward a voltage level of V.sub.pp +V.sub.TM4. During these additional first half-cycles of V.sub.ps, the new V.sub.121 and V.sub.123 can be mathematically represented by the following equation: EQU V.sub.121(new) =V.sub.ps (C/(C+C.sub.121))+V.sub.123(old) -V.sub.TM6
V.sub.123(new) =V.sub.121(new) -V.sub.TM5
where V.sub.121(new) and V.sub.123(new) are the new voltages V.sub.121 and V.sub.123, which relate to the new full-cycle of V.sub.ps. V.sub.121(old) and V.sub.123(old) relate to the voltages V.sub.121 and V.sub.123 from the preceding full cycle of V.sub.ps.
During the increase in the intermediate voltages V.sub.121 and V.sub.123, the switch output voltage level V.sub.out can be mathematically represented by the following equation: EQU V.sub.out =V.sub.123(new) -V.sub.TM3
where V.sub.TM3 is the threshold voltage for transistor M.sub.3. After a certain number of full cycles of V.sub.ps, V.sub.123(new) will reach its maximum voltage of V.sub.pp +V.sub.TM4 which in turn raises the switch output voltage level to its high voltage output level V.sub.pp. V.sub.out can be mathematically described by the following equation: EQU V.sub.out =V.sub.pp +V.sub.TM4 -V.sub.TM3 =V.sub.pp
where threshold voltages V.sub.TM3 and V.sub.TM4 of M.sub.3 or M.sub.4 are approximately equal in this embodiment of the present invention.
To clamp V.sub.123 at V.sub.pp +V.sub.TM4, the desired high voltage value, the clamping diode transistor M.sub.4, whose gate and drain electrodes are electrically coupled to node 123, will discharge any V.sub.123 voltage levels, which are in excess of V.sub.pp +V.sub.TM4.
During the read mode, when a read voltage V.sub.cc is applied to the memory cells containing the programmed "0" logic state, those memory cells will conduct heavily and lower the bit line voltage level to a low voltage level. Alternatively, when a read voltage V.sub.cc is applied to the memory cells containing the erased "1" logic state, the memory cell will not conduct, thereby leaving the bit line at a high voltage level. To determine whether the memory cell is in a "1" logic state or a "0" logic state, a sensing scheme is attached to the memory cell bit line in order to detect these changes in the bit line voltage level.
With the speed of programming a non-volatile memory circuit dependent upon the speed of the decoders, it is always desirable to modify the conventional high voltage switches in order to further increase the ramp rate period for ramping up the high voltage switch voltage level from a low to a high voltage. In addition, since each type of non-volatile memory circuit possesses different voltage characteristics, it also is desirable for the high voltage switch to be able to be optimized for the different applications, which require different high voltage switch ramp rates.
What, therefore, is needed is a system for increasing the ramp rate of a high voltage NMOS switch and for maintaining a ramp rate, which can be adjusted for different applications.